The present invention relates to a data processing system channel which receives and transmits data frames over a data link, and more particularly relates to an apparatus for constructing data frames for transmission over the data link.
It is well known that data messages transmitted over a data link in a data processing system are preceded and followed by header and trailer fields for specifying the contents of the data message. These header and trailer fields typically are made up of special characters which may be independently recognized by a receiver of the message. In high speed data links, it is desirable to construct the header and trailer fields using special purpose hardware, while controlling transmission of data with a channel processor.
U.S. Pat. No. 4,006,465 issued Feb. 1, 1977 for "Apparatus For Control and Data Transfer Between a Serial Data Transmission Medium and a Plurality of Devices" to Cross et al, discloses an apparatus under a microprocessor control for use in communicating over a serial communication loop with a remote attached control unit. The disclosed apparatus is capable of establishing frame synchronization, interpreting commands, assembling data and transmitting bits on the loop. For output operations to a device, the microprocessor loads the device address and a device command or data into shift registers, and initiates the transfer by setting a latch.
U.S. Pat. No. 4,241,398 issued Dec. 23, 1980 for "Computer Network, Line Protocol System" to Carll, discloses a low overhead line protocol format for controlling the asynchronous exchange of digital signal information between a central processing unit and one or more remote processing units of a supervisory control system. Digital signal information is converted into serial bits and organized into bit cells in the information field of one or more serial data frames of a message unit, each frame including a header field and a trailer field.
U.S. Pat. No. 4,284,953 issued Aug. 18, 1981 for "Character Framing Circuit" to Hepworth et al, discloses a digital logic circuit which provides character framing for a continuous stream of synchronous serial data characters.
U.S. Pat. No. 4,675,864 issued Jun. 23, 1987 for "Serial Bus System" to Bliek et al, discloses a serial bus system in which frames are sent from a central station to a plurality of substations over a first conductor, and information is sent from the substation to the central station over a second conductor. Each transmitted frame contains bits identifying whether it is for address, data or a command.